The present invention generally relates to semiconductor memory devices and methods of manufacturing the same and, more particularly, to highly integrated dynamic memory devices and methods of manufacturing the same.
FIGS. 1A and 1B illustrate a memory cell having a MINT architecture and a 0.25 micron design rule which is usable in a 256 Mbit dynamic random access memory (DRAM) device. Specifically, FIG. 1A is a top-down view of the trench memory cell and FIG. 1B is a cross-sectional view taken along line A-Axe2x80x2 of FIG. 1A. DRAM cell 550 includes a trench capacitor 555 and a MOS transfer gate 560. Trench capacitor 555 includes a first N+-type polycrystalline silicon fill 565, a second polycrystalline silicon fill 567, and a collar oxide 571. Transfer gate 560 includes N-type source/drain and drain/source regions 573 and 574 formed in P-type well 575 and a WSix/polycrystalline silicon gate 577 insulatively spaced from the channel region between source/drain region 573 and drain/source region 574. A bit line contact 579 formed in an opening in an insulating layer 80 (of BPSG, for example) and in insulating layer 578 (of silicon nitride, for example) electrically connects source/drain region 573 to bit line 581. A shallow trench isolation (STI) structure 590 electrically isolates DRAM cell 550 from an adjacent DRAM cell and passing word line 592. Passing word line 592 has a WSix/polycrystalline silicon structure. A dielectric layer 587 is formed on bit line 581 and aluminum wirings 589 are formed on dielectric layer 587. One of the aluminum wirings 589 is connected to bit line 581 by a contact stud 591 of tungsten, for example. A diffusion region 583 electrically connects third polycrystalline silicon fill 569 and drain/source region 574 of MOS transfer gate 560. This diffusion region is formed by outdiffusing dopants from the highly doped polycrystalline silicon fill in the storage trench into P-well 575. Diffusion region 583 and third polycrystalline silicon fill 569 constitute a buried strap for connecting trench capacitor 555 to transfer gate 560.
While the memory cell structure of FIGS. 1A and 1B has been successfully applied to 256 Mbit DRAM devices, certain problems can adversely impact the manufacturing yield of such devices. With reference to FIG. 2A, the outdiffusion of dopants to form diffusion region 583 must be carefully controlled. If the dopants diffuse too far into the semiconductor substrate, the operation of transfer gate 550 can be adversely affected. This, for example, places certain limitations on the thermal processes used in the manufacturing process since long, high temperature processes will cause a greater outdiffusion of the dopants. In addition, various crystal defects can be generated at the intersection of the active area (transfer gate) and the deep trench. For example, various oxidation processes during the manufacturing process can cause expansion of the collar oxide 571. This expansion can lead to dislocations in the silicon. In addition to contributing to the adverse operation of the transfer gate, such dislocations can cause junction leakage from the buried strap diffusion layer 583. Still further, as shown in FIG. 2B, in some cases, there can be a discontinuity between the cell array junction and the buried strap caused by ion implantation shadowing due to a passing word line.
Problems are also associated with the scaling-down of the DRAM cell of FIGS. 1A and 1B to form more highly integrated memory devices (e.g., 1 Gbit and 4 Gbit DRAM devices). In particular, the scaled-down memory cell must nonetheless provide a capacitor having a size (i.e., a capacitance) for storing a charge which is sufficient to ensure that data may be correctly written to and read out from the memory cell. Since scaling-down generally results in a shrinking of the horizontal dimensions of the memory cell, one possible way to provide a sufficiently-sized capacitor would be to increase the depth of the trench within which the capacitor is formed. In this way, the horizontal dimensions of capacitor may be scaled down while providing a capacitor of the same size or at least scaled down to a lesser degree. However, the high aspect ratios associated with such deep trenches create difficulties in the processes needed to fill the trenches. In short, to increase the size of trench capacitor 555 during scale-down, either the depth of the trench or the horizontal dimensions of the trench must be increased. Since increasing the depth suffers from processing problems as described above and since increasing the horizontal dimensions is contrary to scaling-down goal, it is difficult to increase the integration density of memory cells having the memory cell structure shown in FIGS. 1A and 1B for new generations memory devices.
One solution to this scaling-down problem is to overlap the transistor area and the deep trench area. Such a transistor over capacitor (TOC) arrangement is shown in U.S. Pat. No. 4,649,625 to Lu, which is incorporated herein by reference. In this structure, the transfer gate is formed on epitaxial silicon which has been laterally grown over an insulator formed on the deep trench. Such laterally grown epitaxial silicon often suffers from defects which can adversely affect the operating characteristics of the transistor and thus of the memory cell itself.
It would be desirable to provide semiconductor memory devices and methods of manufacturing the same which overcome these and other problems.
A semiconductor memory device according to a first aspect of the present invention includes a semiconductor substrate, a first semiconductor region of a first conduction type formed on the semiconductor substrate, and a second semiconductor region of a second conduction type opposite to the first conduction type, formed on the first semiconductor region. A trench capacitor having a trench extending through the first semiconductor region and the second semiconductor region is formed such that its top does not reach a top surface of the second semiconductor region, the trench being formed therein with a conductive trench fill. A pair of gate electrodes are formed on the second semiconductor region, each positioned overlying the trench capacitor. A pair of insulating layers are formed to cover each of the pair of gate electrodes. A conductive layer is formed between the pair of insulating layers to self-align to each of the pair of insulating layers. The conductive layer has a leading end insulated from the second semiconductor region and reaching the interior of the second semiconductor region, and is electrically connected to the conductive trench fill of the trench capacitor. A pair of third semiconductor regions of the first conduction type are formed in the second semiconductor region, and positioned opposite to each other with respect to the conductive layer. Each of the third semiconductor regions is directly in contact with the conductive layer, and constitutes either a source or a drain of transistors having one of the pair of gate electrodes, respectively. The pair of third semiconductor regions is formed substantially to a uniform depth.
A semiconductor memory device according to a second aspect of the present invention includes a semiconductor substrate, a plurality of trench capacitors formed in the semiconductor substrate and arranged at a regular pitch, and a semiconductor layer formed on the semiconductor substrate in which the trench capacitors are formed. A element isolation insulating film is buried in the semiconductor layer to define a plurality of active element areas each spreading over two adjacent trench capacitors. A plurality of transistors are formed two by two in each of the active element areas, such that two transistors share one of source/drain diffusion layers, and the other of the source/drain diffusion layers is positioned over regions of two adjacent trench capacitors. Each of the transistors has a gate connected to a word line continuous in one direction. A contact layer is provided for connecting the other of the source/drain diffusion layers of each of the transistors to a capacitor node layer of corresponding one of the trench capacitors. A bit line is provided to intersect the word lines and connected to one of the source/drain diffusion layers of the transistor.
In the present invention, specifically, (a) the trench capacitors are shaped substantially in a square having one side sized to be 2F, where F is a minimum processing dimension, the diagonals of the squares are oriented in two orthogonal directions of the word line and the bit line, and the trench capacitors are arranged at a regular pitch of 1F or less in directions of two orthogonal sides of the squares, or (b) the trench capacitors are shaped substantially in a square having one side sized to be 2F, where F is a minimum processing dimension, the sides of the squares are oriented in two orthogonal directions of the word line and the bit line, and the trench capacitors are arranged at a regular pitch of 2F in the bit line direction, and shifted sequentially at a one-half pitch on adjacent bit lines.
In the trench capacitors arranged in either (a) or (b) pattern, the active element areas are arranged at a regular pitch in the bit line direction and sequentially shifted at a one-quarter pitch on adjacent bit lines.
In the present invention, the contact layer is buried in the semiconductor layer for connecting a diffusion layer of a transistor to a capacitor node layer of a trench capacitor. For a specific form of the contact, the following approaches may be used.
(1) The contact layer is formed such that it is buried to reach the capacitor node layer, extending through the transistor diffusion layer, after the transistor has been formed;
(2) The semiconductor layer forming the active element areas includes first and second epitaxially grown layers. Then, the contact layer is formed such that it is buried in the first epitaxially grown layer to reach the capacitor node layer before the second epitaxially grown layer is formed. The transistor diffusion layer is formed after the second epitaxially grown layer has been formed such that its bottom surface is connected to the top surface of the contact layer.
(3) The contact layer is formed such that it is buried in the semiconductor layer to reach the capacitor node layer before the transistor is formed. The transistor diffusion layer is connected to the contact layer through a buried diffusion layer formed in an upper side portion of the contact layer.
(4) The contact layer is formed such that it is buried in the semiconductor layer to reach the capacitor node layer before the transistor is formed. The transistor diffusion layer is connected to the top surface of the contact layer through a connection conductor formed on the surface thereof.
In the second aspect of the present invention, the trench capacitor specifically includes a buried plate comprised of a conductive layer having the conduction type opposite to that of the semiconductor substrate, formed in the substrate by diffusion from a trench surface. When the buried plate is formed such that its top end is positioned below the surface position of the semiconductor substrate, a collar insulating film must be formed over the trench capacitor to prevent a parasitic transistor or the like from operating. Accordingly, the capacitor contact layer must also be buried in two stages.
Alternatively, the buried plate may be formed up to the surface of the semiconductor substrate. In this structure, the trench capacitor may be implemented in a simple structure in which a capacitor insulating film is formed over the entire inner wall of the trench and a contact layer is buried in one step. This simplifies the process, and increases the effective area of the trench capacitor, so that a larger allowance can be provided for misalignment when contact holes are subsequently formed.
When the surface strap feature (4) is employed, a constant positional offset must be provided between the contact layer buried on the capacitor node layer and the transistor diffusion layer formed thereon such that they partially overlap. For this purpose, when the active element area is laid out such that its center passes the center of the corresponding trench capacitor, by way of example, the contact layer is formed at a position shifted from the center of the trench capacitor in the word line direction. Alternatively, when the contact layer is positioned at the center of the trench capacitor, the active element area is disposed such that its center is shifted from the center of the trench capacitor in the word line direction.
Also, in the present invention, the trench capacitors are covered with a cap insulating film when a semiconductor layer is epitaxially grown thereon. For this reason, a polycrystalline semiconductor layer is grown on the trench capacitor region. Thus, when wells are formed in the active element areas prior to the formation of transistors, it is preferable that the boundary between the wells does not come in contact with the polycrystalline semiconductor layer. Specifically, a junction leakage can be reduced by forming a pn junction surface formed between a well and the buried plate of the trench capacitor above the polycrystalline layer region.
In the present invention, the semiconductor layer may be comprised of a bulk semiconductor layer of another semiconductor substrate bonded to the semiconductor substrate in which capacitors are formed, and an epitaxially grown layer formed on the bulk semiconductor layer. In this case, a contact layer for connecting the transistor diffusion layer to the capacitor node layer is formed such that it is buried in the bulk semiconductor layer to reach the capacitor node layer before the epitaxially grown layer is formed. Then, the source/drain diffusion layers are formed after the epitaxially grown layer has been formed, such that the bottom surface thereof is connected to the top surface of the contact layer.
Also, when the substrate bonding technique is used, a substrate isolation insulating film is preferably interposed between the bonding surfaces of the substrates. Then, the element isolation insulating film is comprised of a first element isolation insulating film buried in element isolation regions in the bit line direction to a depth at which the first element isolation insulating film reaches the substrate isolation insulating film; and a second element isolation insulating film partially overlapping the first element isolation insulating film and buried in the element isolation regions in the bit line direction and word line direction to a depth shallower than the first element isolation insulating film.
A semiconductor device according to a third aspect of the present invention includes a semiconductor substrate, an element isolation insulating film including a first insulating film buried to define active element areas on the semiconductor substrate, and a second insulating film shallower than the first insulating film; and elements formed in the active element areas defined by the element isolation insulating film.
A method of manufacturing a semiconductor memory device according to a fourth aspect of the present invention includes the steps of forming a plurality of trench capacitors arranged at a regular pitch on a semiconductor substrate with a capacitor node layer being covered with a cap insulating film, wherein the cap insulating film has a surface positioned below a surface of the semiconductor substrate, epitaxially growing a semiconductor layer on the semiconductor substrate on which the trench capacitors have been formed, forming an element isolation insulating film on the semiconductor layer to define a plurality of active element areas such that each active element area spreads over two adjacent trench capacitors, forming two transistors in each of the active element areas such that two transistors share one of source/drain diffusion layers, the other of the source/drain diffusion layers is positioned over regions of two adjacent trench capacitors, and gate electrodes serve as word lines continuous in one direction, burying a contact layer between the gate electrodes, extending through the other of the source/drain diffusion layers to reach the capacitor node layer, and forming bit lines connected to one of the source/drain diffusion layers to intersect the word lines.
A method of manufacturing a semiconductor memory device according to a fifth aspect of the present invention includes the steps of forming a plurality of trench capacitors arranged at a regular pitch on a semiconductor substrate with a capacitor node layer being covered with a cap insulating film, wherein the cap insulating film has a surface positioned below a surface of the semiconductor substrate, epitaxially growing a first semiconductor layer on the semiconductor substrate on which the trench capacitors have been formed, burying a contact layer in the first semiconductor layer to reach the capacitor node layer, epitaxially growing a second semiconductor layer on the first semiconductor layer in which the contact layer is buried, forming an element isolation insulating film on the second semiconductor layer to define a plurality of active element areas such that each of the active element areas spreads over two adjacent trench capacitors, forming two transistors in each of the active element areas such that two transistors share one of source/drain diffusion layers, the other of the source/drain diffusion layers is connected to a top surface of the contact layer, and gate electrodes serve as word lines continuous in one direction, and forming bit lines connected to one of the source/drain diffusion layers to intersect the word lines.
A method of manufacturing a semiconductor memory device according to a sixth aspect of the present invention includes the steps of forming a plurality of trench capacitors arranged at a regular pitch on a semiconductor substrate with a capacitor node layer being covered with a cap insulating film, wherein the cap insulating film has a surface positioned below a surface of the semiconductor substrate, epitaxially growing a semiconductor layer on the semiconductor substrate in which the trench capacitors have been formed, burying a contact layer in the semiconductor layer to reach a capacitor node layer of the trench capacitors, the contact layer having an upper end portion connected to an impurity diffusion layer formed in the semiconductor layer, forming an element isolation insulating film on the semiconductor layer to define a plurality of active element areas such that each of the active element areas spreads over two adjacent trench capacitors, forming two transistors in each of the active element areas such that two transistors share one of source/drain diffusion layers, the other of the source/drain diffusion layers is connected to the contact layer through the impurity diffusion layer, and gate electrodes serve as word lines continuous in one direction, and forming bit lines connected to one of the source/drain diffusion layers to intersect the word lines.
A method of manufacturing a semiconductor memory device according to a seventh aspect of the present invention includes the steps of forming a plurality of trench capacitors arranged at a regular pitch on a semiconductor substrate with a capacitor node layer being covered with a cap insulating film, wherein the cap insulating film has a surface positioned below a surface of the semiconductor substrate, epitaxially growing a semiconductor layer on the semiconductor substrate on which the trench capacitors have been formed, burying a contact layer in the semiconductor layer to reach a capacitor node layer of the trench capacitors, forming an element isolation insulating film on the semiconductor layer to define a plurality of active element areas such that each of the active element areas spreads over two adjacent trench capacitors, forming two transistors in each of the active element areas such that two transistors share one of source/drain diffusion layers, the other of the source/drain diffusion layers is positioned on the trench capacitor region, and gate electrodes serve as word lines continuous in one direction, forming a surface connection conductor for connecting the other of the source/drain diffusion layers to the contact layer corresponding thereto, the surface connection conductor being self-aligned to the word lines, and forming a bit line connected to one of the source/drain diffusion layers to intersect the word line.
A method of manufacturing a semiconductor memory device according to an eighth aspect of the present invention includes the steps of forming a plurality of trench capacitors arranged at a regular pitch on a semiconductor substrate with a capacitor node layer being covered with a cap insulating film, forming a first semiconductor layer by bonding another semiconductor substrate through a substrate isolation insulating film to the semiconductor substrate in which the trench capacitors are formed, burying a contact layer in the first semiconductor layer to reach the capacitor node layer, epitaxially growing a second semiconductor layer on the first semiconductor layer in which the contact layer is buried, forming an element isolation insulating film on the first and second semiconductor layers to define a plurality of active element areas such that each of the active element areas spreads over two adjacent trench capacitors, forming two transistors in each of the active element areas such that two transistors share one of source/drain diffusion layers, the other of the source/drain diffusion layers is connected to a top surface of the contact layer, and gate electrodes serve as word lines continuous in one direction, and forming a bit line connected to one of the source/drain diffusion layers to intersect the word line.
According to the present invention, the formation of transistors in a semiconductor layer formed on a substrate, in which trench capacitors are buried, enables the trench capacitors to be most closely populated to maximally increase the area occupied thereby. This also results in a lower aspect ratio when the trench capacitors are formed, increased capacitor areas, and a resulting larger allowance for misalignment of a transistor to a connection.
These and other features and advantages of the present invention will be better understood from a reading of the following detailed description in conjunction with the accompanying drawings.